In association with the progressive size reduction of electronic equipment in recent years, the electronic components used in such electronic equipment continue to be further reduced in size as well. The same pattern can be witnessed with semiconductor packages, where the ball-grid array (BGA) is drawing attention because of its small size and ease of mounting advantage over other packages coping with a large increase in number of terminal pins.
Among the BGA type packages, those using ceramic substrate are superior in their ease of face-down mounting and heat dissipation characteristics, and are thus most suitable for further miniaturization of packages especially for LSI's which dissipate a large quantity of heat due to high speed signal transmission in devices such as microprocessors.
As disclosed in Japanese Laid-Open Patent Hei 8-88297, a ceramic type BGA package (C-BGA) is composed of a ceramic multi layer wiring substrate joined with solder balls. FIG. 18 shows a conventional packaging substrate. In FIG. 18, C-BGA package 101 is composed of a multi layer ceramic circuit substrate 102 joined with two or more types of solder balls 106 with different melting points for connection.
In this example of a conventional packaging substrate, when experiencing thermal hysteresis resulting from environmental changes, stress and strain are caused in the solder balls due to the difference in thermal expansion between the ceramic package and printed circuit board. The use of two or more types of solder balls is to solve the problem of low reliability of connection such as breakage of connecting parts owing to thermal fatigue resulting from stress or strain, or breakage of the ceramic package itself due to stress.
In order to make a multilayer ceramic circuit substrate 102 in this method, it is necessary to prepare several pieces of green sheets composed mainly of alumina as the base material; form via holes on each of the sheets; form a wiring pattern; and fill the via holes with a conductive paste. A ceramic multi layer circuit substrate 102 is obtained by integrating each green sheet on which the wiring pattern has been formed through the laminating, heating and pressurizing processes.
As another conventional example, a method of manufacturing a ceramic packaging substrate in which fine wiring is formed on a ceramic substrate is disclosed in Japanese Laid-Open Patent Hei 7-202381. As the process is shown in FIG. 19, a conductive layer 202 is formed by printing on the entire surface of a ceramic substrate 201, followed by forming an anti-sandblast resin pattern 203 on that part of the surface of the conductive layer where a conductor pattern is to be formed by a photo-lithography process, and forming a conductor pattern 204 by peeling off the anti-sandblast resin pattern after removing by sand-blasting processing the portion of the conductive layer where the aforesaid anti-sandblast resin pattern has not been formed. In this method, blotting of the conductor pattern, which usually occurs with screen printing method, does not occur. Also, there is no dispersion of the height of the conductor pattern depending on locations and the flatness of the top portions of the pattern obtained is superior.
However, the conventional example described first has the following problems.
1) Since the formation of a wiring pattern is made by screen printing, it is extremely difficult to simultaneously make both the line width (W) and the line spacing (S) smaller than 75 μm.
2) When forming a wiring pattern by screen printing, the finer the pattern the thinner the film becomes. As an example, when W=75 μm, the film thickness obtained will be only 5 μm resulting in a high wiring resistance.
3) Especially when tungsten is used as the wiring material, the wiring resistance will be 3 to 5 times higher than that of silver and copper. As the pattern gets finer, this disadvantage becomes more conspicuous, in some cases making the use as electronic components impractical.
4) As the substrate and wiring material are simultaneously fired at such high temperatures as approximately 900 to 1,600° C., material shrinkage of approximately 15-20% occurs after the firing, thereby causing a large dispersion in the dimensions of the substrate. The dispersion of shrinkage causes a large dispersion in the dimension of the wiring, leading to inaccuracy of connection with the very fine bumps of a LSI and to a lowered yield of packaging.
5) Furthermore, in the case of forming of wiring pattern by screen printing, the line width becomes wider than 75 μm (generally 120 μm or greater is necessary when yield of printing and wiring resistance are taken into account). In order to form many lines in a narrow area, it is necessary to adopt a multi layer configuration of wiring, and as the number of layers increases and the dimensional precision becomes tighter to secure precision in mounting, the cost of the substrate increases.
On the other hand, the second example of the conventional method has the following problems.
1) Since a conductive layer is individually formed by printing on the entire surface of a ceramic substrate and then that part of the conductive layer where the aforementioned anti-sandblast resin pattern is not formed is removed by sandblasting, loss of expensive conductor material is large which is problematic from the standpoint of effective usage of resources, productivity is low due to dependence on the time-consuming process of sandblasting, resulting in a cost increase in the packaging substrate.
2) Also, as the process of individually forming an anti-sandblast resin pattern on a ceramic substrate by the use of photolithography includes the processes of film formation, exposure, and developing, it has the disadvantage of low productivity even though the precision is high.
3) A wiring pattern can be finely formed by photolithography, however, with the sandblasting method of removing a conductive layer, a desired wiring pattern cannot be obtained unless the thickness of the conductive layer is made thinner as the wiring pattern is made finer. For example, when forming a wiring with a line width of W=30 μm, thickness of the conductive layer should be approximately 10 μm or smaller in order to obtain a desired line width. Consequently, this example, too, has the disadvantage of a high wiring resistance, making it inappropriate for most C-BGA's, especially for large-size C-BGA.